1. Field of the Invention
The present invention relates to an integrated circuit having a voltage boosted above a given power supply level.
2. Description of the Prior Art
In the design of integrated circuits, it is frequently desirable to boost the voltage on a circuit node to a value in excess of a power supply voltage. For example, in the case of 5 volt integrated circuits, a boosted level of about 6 to 7 volts is often generated. The boosted level is applied to the gates of transistors that serve as clock drivers, or row drivers in the case of static or dynamic memory chips. In this manner, the threshold voltage drop of the transistor, typically in the range of from 0.5 to 2 volts, is overcome by the boosted voltage, and a more robust clock or row voltage is obtained for improved circuit operation. In still another application, a substrate voltage is boosted by means of a so-called back gate bias generator. For example, a negative boost voltage has been used to bias a substrate to a voltage below V.sub.SS, typically to increase transistor thresholds and reduce circuit capacitance.
In prior-art boost circuits implemented in CMOS technology, an n-channel transistor was used for boosting positive voltages (above V.sub.DD), whereas a p-channel transistor was used for boosting negative voltages (below V.sub.SS). One example of n-channel boost circuitry used in a dynamic memory is shown in U.S. Pat. No. 4,649,523 coassigned herewith, with still other circuit types being possible. This use of n-channel devices connected to a boosted positive node prevents forward-biasing the junction between the source or drain region of the transistor and the semiconductor region in which it was formed. That is, a positive voltage on an n-type drain region reverse-biases the junction between the drain and the underlying p-type region. Otherwise, any forward-biased conduction between the drain and the underlying region could cause undesirable effects in the operation of the integrated circuit. For example, the conduction would load down the boost circuitry, wasting power. Also, the conduction could inject undesirable carriers into the underlying region, which could lead to latch-up in CMOS circuits. However, it is apparent that this restriction limits design freedom to the use of only one conductivity type source/drain region connected to a given type of boosted node.
The underlying region in which the source/drain regions are formed is often, but not necessarily, a "tub" (alternatively referred to as a "well") region that is doped separately than the rest of the substrate. Twin-tub CMOS processes are known in the art, wherein both the n-channel and p-channel devices are formed in tubs, being p-tubs and n-tubs respectively. Alternatively, single-tub CMOS processes are known, wherein only one type of device is formed in the tub, and the other type is formed in the surrounding substrate region. More recently, triple-tub processes have been used, whereby tubs having two different doping levels are used for one device type (typically the n-channel transistors), and another tub for the other device type (typically the p-channel transistors). In the prior art, an n-tub is usually electrically connected to the positive power supply voltage (V.sub.DD), whereas a p-tub is usually connected to the negative power supply voltage (V.sub.SS). Therefore, any voltage on a source/drain region of a p-channel device that is more than one diode voltage drop (about 0.6 volts) above V.sub.DD causes conduction to the n-tub. Similarly, any voltage on a source/drain region of an n-channel device more than one diode voltage drop below V.sub.SS causes conduction to the p-tub.